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5.- Configurazione del processore.
E' importante, prima di iniziare ad utilizzare il processore, configurarne
le risorse di base.
Questa operazione è relativa a ciascun processore o famiglia, in quanto le
risorse interne potranno essere molto differenti.
;********************************************************************
;====================================================================
; CONFIGURAZIONE
;====================================================================
#if DEBUG == 1
; debug configuration
__CONFIG _CONFIG1, _FOSC_INTOSC & _WDTE_OFF & _PWRTE_OFF & _MCLRE_ON
__CONFIG _CONFIG1, _CP_OFF & _CPD_OFF & _BOREN_OFF & _CLKOUTEN_ON
__CONFIG _CONFIG1, _IESO_OFF & _FCMEN_OFF
__CONFIG _CONFIG2, _WRT_OFF & _PLLEN_OFF & _STVREN_OFF & _BORV_19
__CONFIG _CONFIG2, _LVP_OFF
#else
; standard configuration
__CONFIG _CONFIG1, _FOSC_INTOSC & _WDTE_OFF & _PWRTE_ON & _MCLRE_ON
__CONFIG _CONFIG1, _CP_ON & _CPD_ON & _BOREN_ON & _CLKOUTEN_OFF
__CONFIG _CONFIG1, _IESO_OFF & _FCMEN_OFF
__CONFIG _CONFIG2, _WRT_OFF & _PLLEN_OFF & _STVREN_OFF & _BORV_19
__CONFIG _CONFIG2, _LVP_OFF
#endif |
La configurazione non è parte secondaria del programma, dato che tanto più è
complesso il processore tanto più è necessario verificare cosa sia attivato e
cosa no nei default.
Per evitare questo è molto più pratico inserire un CONFIG completo:
non costa nulla, non rallenta l' assemblaggio ed evita sorprese sgradevoli e
situazioni difficili da debuggare.
Vediamo un esempio di "tutorial" minimalista relativo alle
opzioni possibili del CONFIG e ad una diversa espressione delle alternative di
configurazione per un PIC18F.
Una direttiva dell' assembler NOLIST blocca la stampa nel file
listato (.LST) della
parte solo descrittiva; la stampa viene ripresa dopo la direttiva LIST.
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NOLIST
;=============================================================================
; CONFIGURAZIONE =
;=============================================================================
;-----------------------------------------------------------------------------
; Funzioni possibili in CONFIG
;-----------------------------------------------------------------------------
; PORTB A/D Enable bit:
; PBADEN = DIG ; PORTB<4:0> as digital I/O
; PBADEN = ANA ; PORTB<4:0> as analog input
;
; CCP2 MUX bit:
; CCP2MX = RB3 ; CCP2 input/output is multiplexed with RB3
; CCP2MX = RC1 ; CCP2 input/output is multiplexed with RC1
;
; Extended Instruction Set Enable bit:
; XINST = OFF ; Instruction set extension disabled (Legacy mode)
; XINST = ON ; Instruction set extension enabled
;
; Background Debugger Enable bit:
; DEBUG = ON ; Background debugger enabled, RB6 and RB7 are
dedicated
; DEBUG = OFF ; Background debugger enabled, RB6 and RB7 as GPIO
;
; Single-Supply ICSP Enable bit:
; LVP = OFF ; Single-Supply ICSP disabled
: LVP = ON Single-Supply ICSP enabled
;
; Oscillator Selection bits:
; OSC = HS ; Oscillatore principale
; OSC = LP ; LP
; OSC = XT ; XT
; OSC = HS ; HS
; OSC = RC ; External RC , CLKO on RA6
; OSC = EC ; EC , CLKO on RA6
; OSC = ECIO ; EC , GPIO on RA6
; OSC = HSPLL ; HS , PLL enabled (Clock Frequency = 4 x FOSC1)
; OSC = RCIO ; External RC , GPIO on RA6
; OSC = INTIO2 ; Internal oscillator, GPIO on RA6 and RA7
; OSC = INTIO1 ; Internal oscillator, CLKO on RA6, GPIO on RA7
;
; Low-Power Timer1 Oscillator Enable bit:
; LPT1OSC = OFF ; Timer1 for higher power operation
; LPT1OSC = ON ; Timer1 for low-power operation
;
; Fail-Safe Clock Monitor Enable bit:
; FCMEN = OFF ; Fail-Safe Clock Monitor disabled
; FCMEN = ON ; Fail-Safe Clock Monitor enabled
;
; Internal/External Oscillator Switchover bit:
; IESO = OFF ; Oscillator Switchover mode disabled
; IESO = ON ; Oscillator Switchover mode
enabled
;
; Power-up Timer Enable bit:
; PWRT = ON ; PWRT enabled
; PWRT = OFF ; PWRT disabled
;
; Brown-out Reset Enable bits:
; BOR = ON ; enabled in hardware only -
SBOREN disabled
; BOR = OFF ; disabled in hardware and
software
; BOR = SOFT ; enabled and controlled SBOREN
; BOR = NOSLP ; enabled in hrdwr only, disabled in Sleep
mode
;
; Brown-out Reset Voltage bits:
; BORV = 0 ; Soglia reset 4.5V
; BORV = 1 ; Soglia reset 4.2V
; BORV = 2 ; Soglia reset 2.7V
; BORV = 3 ; Soglia reset 2.0V
;
; MCLR Pin Enable bit:
; MCLRE = OFF ; RE3 input pin enabled, MCLR disabled
; MCLRE = ON ; MCLR pin enabled, RE3 input pin disabled
;
; Watchdog Timer Enable bit:
; WDT = OFF ; WDT disabled - control by SWDTEN bit
; WDT = ON ; WDT enabled
;
; Watchdog Timer Postscale Select bits:
; WDTPS = 1 ; 1:1
; WDTPS = 2 ; 1:2
; WDTPS = 4 ; 1:4
; WDTPS = 8 ; 1:8
; WDTPS = 16 ; 1:16
; WDTPS = 32 ; 1:32
; WDTPS = 64 ; 1:64
; WDTPS = 128 ; 1:128
; WDTPS = 256 ; 1:256
; WDTPS = 512 ; 1:512
; WDTPS = 1024 ; 1:1024
; WDTPS = 2048 ; 1:2048
; WDTPS = 4096 ; 1:4096
; WDTPS = 8192 ; 1:8192
; WDTPS = 16384 ; 1:16384
; WDTPS = 32768 ; 1:32768
;
; Stack Full/Underflow Reset Enable bit:
; STVREN = OFF ; will not cause Reset
; STVREN = ON ; will cause Reset
;
; Boot Block Size Select bits:
; BBSIZ = BB256 ; 256 Word
; BBSIZ = BB512 ; 512 Word
; BBSIZ = BB1K ; 1024 Word
;
; Code Protection bit Block 0 and 1 (ON/OFF):
; CPx = ON ; Block x code-protected
; CPx = OFF ; Block x not code-protected
; CP0 = OFF ; code protection block 0
; CP1 = OFF ; code protection block 1
;
; Boot Block Code Protection bit (ON/OFF):
; CPB = OFF ; code protection bootblock off
; CPB = ON ; code protection bootblock on
;
; Data EEPROM Code Protection bit (ON/OFF):
; CPD = OFF ; code protection eeprom disabled
; CPD = ON ; code protection eeprom enabled
;
; Write Protection bit Block 0 and 1 (ON/OFF):
; WRTx = ON ; Block x write-protected
; WRTx = OFF ; Block x not write-protected
; WRT0 = OFF ; Write protect block 0
; WRT1 = OFF ; Write protect block 1
; WRTB = OFF ; Write protect bootblock
;
; Configuration Register Write Protection bit (ON/OFF):
; WRTC = OFF ; Write protecte config. disabled
; WRTC = ON ; Write protecte config. enabled
;
; Data EEPROM Write Protection bit (ON/OFF):
; WRTD = OFF ; Write protect eeprom disabled
; WRTD = ON ; Write protect eeprom enabled
;
; Table Read Protection bit Block 0 and 1 (ON/OFF):
; Block x protected from table reads executed in other blocks
; EBTRx = ON ; table block x protected
; EBTRx = OFF ; table block x not protected
; EBTR0 = OFF ; Read protect table block 0
; EBTR1 = OFF ; Read protect table block 1
;
; Boot Block Table Read Protection bit:
; EBTRB = ON ; Boot block protected
; EBTRB = OFF ; Boot block not protected
LIST
#if DEBUG == 1
; condizionale per configurazione in debug
;======================================================================
; CONFIGURAZIONS IN MODO DEBUG CON PICKIT
;======================================================================
;----------------------------------------------------------------------
; Modificare le linee con le scelte volute
;-----------------------------------------------------------------------
CONFIG
PBADEN = DIG ;
PORTB<4:0> pins as digital I/O on Reset
CONFIG
XINST = OFF ;
Instruction set extension and IA mode disabled
CONFIG
DEBUG = ON
; Background debugger enabled on RB6 and RB7
CONFIG
LVP = OFF
; Single-Supply ICSP disabled
CONFIG
OSC = INTIO1 ;
Internal oscillator, CLKO on RA6, GPIO on RA7
CONFIG
LPT1OSC = OFF ;
Timer1 configured for higher power operation
CONFIG
FCMEN = OFF ;
Fail-Safe Clock Monitor disabled
CONFIG
IESO = OFF
; Oscillator Switchover mode disabled
CONFIG
PWRT = OFF
; PWRT disabled
CONFIG
BOR = ON
; Brown-out in hardware only (SBOREN is disabled)
CONFIG
BORV = 1
; Soglia reset 4.2V
CONFIG
MCLRE = ON
; MCLR pin enabled; RE3 input pin disabled
CONFIG
WDT = OFF
; WDT disabled (control is placed on the SWDTEN bit)
CONFIG
STVREN = ON ;
Stack full/underflow will cause Reset
CONFIG
CP0 = OFF
; code protection block 0 (ON/OFF)
CONFIG
CP1 = OFF
; code protection block 1 (ON/OFF)
CONFIG
CPB = OFF
; code protection bootblock (ON/OFF)
CONFIG
CPD = OFF
; code protection eeprom (ON/OFF)
CONFIG
WRT0 = OFF
; Write protect block 0 (ON/OFF)
CONFIG
WRT1 = OFF
; Write protect block 1 (ON/OFF)
CONFIG
WRTB = OFF
; Write protect bootblock (ON/OFF)
CONFIG
WRTC = OFF
; Write protecte configurations (ON/OFF)
CONFIG
WRTD = OFF
; Write protect eeprom (ON/OFF)
CONFIG
EBTR0 = OFF ;
Read protect table block 0 (ON/OFF)
CONFIG
EBTR1 = OFF ;
Read protect table block 1 (ON/OFF)
CONFIG
EBTRB = OFF ;
Boot block not protected from table reads
#else
;======================================================================
; CONFIGURAZIONS di lavoro
;======================================================================
;----------------------------------------------------------------------
; Modificare le linee con le scelte volute
;-----------------------------------------------------------------------
CONFIG
PBADEN = DIG ;
PORTB<4:0> pins as digital I/O on Reset
CONFIG
XINST = OFF ;
Instruction set extension and IA mode disabled
CONFIG
DEBUG = OFF ;
Background debugger disabled on RB6 and RB7
CONFIG
LVP = OFF
; Single-Supply ICSP disabled
CONFIG
OSC = INTIO1 ;
Internal oscillator, CLKO on RA6, GPIO on RA7
CONFIG
LPT1OSC = OFF ;
Timer1 configured for higher power operation
CONFIG
FCMEN = OFF ;
Fail-Safe Clock Monitor disabled
CONFIG
IESO = OFF
; Oscillator Switchover mode disabled
CONFIG
PWRT = ON
; PWRT enabled
CONFIG
BOR = ON
; Brown-out in hardware only (SBOREN is disabled)
CONFIG
BORV = 1
; Soglia reset 4.2V
CONFIG
MCLRE = ON
; MCLR pin enabled; RE3 input pin disabled
CONFIG
WDT = OFF
; WDT disabled (control is placed on the SWDTEN bit)
CONFIG
STVREN = ON ;
Stack full/underflow will cause Reset
CONFIG
CP0 = ON
; code protection block 0 ON
CONFIG
CP1 = ON
; code protection block 1 ON
CONFIG
CPB = OFF
; code protection bootblock OFF
CONFIG
CPD = OFF
; code protection eeprom OFF
CONFIG
WRT0 = OFF
; Write protect block 0 OFF
CONFIG
WRT1 = OFF
; Write protect block 1 OFF
CONFIG
WRTB = OFF
; Write protect bootblock OFF
CONFIG
WRTC = OFF
; Write protecte configurations OFF
CONFIG
WRTD = OFF
; Write protect eeprom OFF
CONFIG
EBTR0 = OFF ;
Read protect table block 0 OFF
CONFIG
EBTR1 = OFF ;
Read protect table block 1 OFF
CONFIG
EBTRB = OFF ;
Boot block not protected from table reads
#endif
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Certamente se non si ritiene di avere bisogno di un dettaglio simile,
questa parte sarà tagliata a piacere.
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